1. Field of the Invention
The present invention relates toga semiconductor memory device, and more particularly, to a cell array in which data are stored in a semiconductor dynamic random access memory (DRAM). Specifically, the present invention relates to a semiconductor memory device having a memory cell with a vertical transistor and a method of fabricating the same.
2. Description of the Related Art
Numerous methods for increasing the integration density of semiconductor memory devices have been researched. Specifically, methods using a vertical transistor have been researched to reduce the area of a unit cell. However, as the integration density of the devices increases and the operating voltage decreases, a silicon body effect, which is one factor determining the reliability of semiconductor memory devices, becomes more influential in the control of the threshold voltage of devices.
FIG. 1 is a perspective view of some memory cells of a conventional semiconductor memory device using a vertical transistor. FIG. 2 is a plan view of FIG. 1. FIGS. 1 and 2 correspond to FIGS. 2 and 3, respectively, of U.S. Pat. No. 6,072,209.
FIGS. 1 and 2 illustrate two buried bit lines 202 and 204, a pair of word lines 206 and 207, another word line 208, and four memory cells 112a, 112b, 112c and 112d on a semiconductor substrate 210. Each of the bit lines 202 and 204 is defined by isolation trenches 220, 221 and 222 extending top to bottom in FIG. 2 that are filled with an insulating material such as silicon dioxide 224. A vertical transistor 130 is formed in each memory cell. Each vertical transistor 130 contacts a gate insulation layer 218 formed on the sidewall of a word line 206, 207 or 208. Each vertical transistor further includes first source/drain region 212, a body region 214 including a channel region, and a second source/drain region 216, which are formed vertically on the semiconductor substrate 210. The first source/drain region 212 functions as a bit line. A storage electrode 132 of a capacitor is formed on the second source/drain region 216. In such a structure, the body region 214 including the channel region of each memory cell floats completely and is separated from the body regions of the other transistors 130 by the word lines 206, 207 and 208.
In such a prior art structure, each memory cell storing data is very vulnerable to external noise. Generally, a MOS transistor is actuated by a channel region which is formed in the vicinity of the surface of a body region by a voltage applied to a gate electrode. When the body region of the MOS transistor is exposed to external supply voltage noise due to a variety of reasons, the charge of the body region of the transistor changes. In the prior art, body regions float and are separated from one another such that the charge of each transistor is not consistent. Accordingly, when the charge of the body region of each transistor changes due to external noise, the threshold voltage of each MOS transistor changes. Consequently, errors occur during operation, thereby decreasing the reliability of the memory device.
To solve the above problem, it is a first objective of the present invention to provide a semiconductor memory device from which a floating body effect is substantially eliminated and which has enhanced immunity to external noise, and a method of fabricating the same.
It is a second objective of the present invention to provide a semiconductor memory device from which a floating body effect is substantially eliminated and in which a memory cell has a surface area that is minimized to 4F2, and a method of fabricating the same.
Accordingly, to achieve the above objects of the invention, there is provided a semiconductor memory device that does not have a floating body effect. The memory device includes a semiconductor substrate. A plurality of bit lines are buried in the semiconductor substrate such that the surfaces of the bit lines are adjacent to the surface of the semiconductor substrate. The bit lines are arranged to be parallel to one another. A plurality of word lines are formed on the semiconductor substrate so that the word lines cross and are isolated from the bit lines. A plurality of vertical access transistors are formed at individual memory cells where the bit lines and the word lines intersect. Each vertical access transistor includes a first source/drain region, a channel region and a second source/drain region which are formed vertically on a bit line. The vertical access transistor contacts a gate insulation layer formed on part of the sidewall of a word line. Body regions including the channel regions of the access transistors are connected to one another to be a single integrated (electrically interconnected) region.
Preferably, the semiconductor memory device is a cell array for a dynamic random access memory, and a storage electrode of a capacitor is formed on the second source/drain region of each access transistor. The body regions of the access transistors may be formed by a single deposition process and a patterning process, thereby forming a single integrated body. Alternatively, the body regions of the access transistors may be isolated from one another by the word lines but connected to one another by a bridge-like connector so that they are integrated. An insulation layer having the same thickness as that of the gate insulation layer is formed on the sidewall of each word line. Preferably, the word line at which each access transistor is formed has a quadrilateral shape of which one side is open in a plan view, and the channel region of the access transistor is formed within the quadrilateral shape.
To achieve the above objects of the invention, in a first embodiment, there is provided a semiconductor memory device including a semiconductor substrate on which trench regions filled with an insulating material are arranged at predetermined intervals. A plurality of bit lines are arranged parallel to one another between the trench regions on the semiconductor substrate. A plurality of word lines extend on the trench regions of the semiconductor substrate so that the word lines cross the bit lines. The sidewall and the top of each word line are covered with an insulating material. A plurality of vertical access transistors are formed at individual memory cells where the bit lines and the word lines intersect. Each vertical access transistor includes a first source/drain region, a channel region and a second source/drain region which are formed vertically on a bit line. The vertical access transistor contacts a gate insulation layer formed on part of the sidewall of a word line. A single monolithic body region or integrated plural body regions includes adjacent body regions that are insulated from the word lines. The adjacent body regions including the channel regions are isolated by the word lines but are integrated through (over) the top of the insulating material on the word lines.
In a second embodiment, there is provided a semiconductor memory device including a semiconductor substrate on which trench regions filled with an insulating material are arranged at predetermined intervals. A plurality of bit lines are arranged parallel to one another between the trench regions on the semiconductor substrate. A plurality of word lines extend on the trench regions of the semiconductor substrate so that the word lines cross the bit lines. The sidewall of each word line is covered with an insulating material. A plurality of vertical access transistors are formed at individual memory cells where the bit lines and the word lines intersect. Each vertical access transistor includes a first source/drain region, a body region including a channel region and a second source/drain region which are formed sequentially overlying one of the bit lines. The vertical access transistor contacts a gate insulation layer formed on one side of the sideswalls of the word lines. A plurality of body regions are formed to be insulated from the word lines. A connector is formed to electrically connect adjacent body regions.
To achieve the above objects of the invention, in the first embodiment, there is provided a method of fabricating a semiconductor memory device. The method includes the step of forming trench regions filled with an insulating material at predetermined intervals. The trench regions are buried in a semiconductor substrate such that they are adjacent to the surface of the semiconductor substrate. A bit line is formed between adjacent trench regions in the semiconductor substrate, and the surface of the semiconductor substrate is planarized to expose the surface of the bit line. A first insulation layer, a conductive layer for a word line and a mask layer of an insulating material are sequentially formed on the entire surface of the planarized semiconductor substrate. A word line having the mask layer is formed on its top surface by performing photolithography. A second insulation layer is formed on the sidewall of the exposed word line. A portion of the surface of the bit line adjacent to the sidewall of the word line is exposed in a region where the word line and the bit line intersect. A first source/drain region material layer is formed on the exposed bit line. A body region material layer is formed on the entire surface of the semiconductor substrate including the first source drain region material layer such that the body region material layer has a predetermined height from the mask layer on the word line. A portion of the body region material layer is etched using photolithography so that the body region material layer corresponds to the first source/drain region material layer. A second source/drain material layer is formed on the etched and exposed body region material layer.
In the second embodiment, there is provided a method of fabricating a semiconductor memory device. The method includes the step of forming trench regions filled with an insulating material at predetermined intervals. The trench regions are buried in a semiconductor substrate such that they are adjacent to the surface of the semiconductor substrate. A bit line is formed between adjacent trench regions in the semiconductor substrate, and the surface of the semiconductor substrate is planarized to expose the surface of the bit line. A first insulation layer and a conductive layer for a word line are sequentially formed on the entire surface of the planarized semiconductor substrate. A word line is formed by photolithography and etching. A second insulation layer is formed on the exposed word line. Part of the surface of the bit line adjacent to the sidewall of the word line is exposed at a portion where the word line and the bit line intersect. A first source/drain region material layer is formed on the exposed bit line. A body region material layer is formed on the entire surface of the semiconductor substrate including the first source drain region material layer such that the body region material layer is higher than the word line. The body region material layer is polished until the surface of the word line is exposed to planarize the surface of the semiconductor substrate. A third insulation layer is formed on substantially the entire surface of the planarized semiconductor substrate. A portion of the third insulation layer is etched by performing photolithography so that the third insulation layer corresponds to the first source/drain region material layer. A portion of the body region material layer is etched using the etched third insulation layer as an etching mask. A second source/drain material layer is formed on the exposed body region material layer.
According to the present invention, body regions of transistors in individual memory cells do not float but are integrated into one so that noise introduced to each memory cell in a memory device can be easily eliminated. As a result, the charge of a body region of each transistor can be maintained constant without being influenced by noise so that malfunction of the transistor can be prevented. In addition, the gate electrode of a vertical transistor is formed to have a quadrilateral shape whose one side is open so that it can be easy to realize a memory cell having an area of 4F2.